1. Field of the Invention
The present invention relates to power management in dynamic logic. More specifically, the present invention relates to a technique that introduces and propagates a null value signal into and through certain areas of NDL dynamic logic to reduce the overall power consumption of the logic, without impacting the timing or performance of the design.
2. Description of the Related Art
Intrinsity Inc. (f/k/a EVSX Inc.), the assignee of this application, has developed a new dynamic logic design style and an associated family of semiconductor devices, originally designated as N-NARY logic, and now known as NDL logic implemented in FAST14 technology. N-NARY dynamic logic circuits (denoted as “NDL gates”), comprise a logic tree circuit that couples to one or more input logic paths and one or more output logic paths. The logic tree circuit is a single, shared bgic tree comprising transistors organized into multiple evaluation paths that evaluate the function of the logic circuit (e.g., an AND/NAND function, an OR/NOR function, or an XOR/Equivalence function, and the like). The logic tree is precharged using a precharge circuit and evaluates using an evaluate circuit, both of which are controlled by a clock signal.
The input and output logic paths in a NDL gate, and indeed, the datapath between successive NDL gates typically do not carry binary signals. Instead. NDL logic uses a new signal structure, a “1-of-N signal”, which is a multi-wire 1-hot signal that conveys a signal value using a specifically defined encoding scheme. NDL logic and 1-of-N signals can be used to build adders, shifters, multipliers, boolean units, RAM devices, and even entire datapaths. Intrinsity's NDL logic and 1-of-N signal technology is illustrated and described in U.S. Pat. No. 6,069,497, entitled “Method and Apparatus for a N-NARY Logic Circuit Using 1 of N Signals” and U.S. Pat. No. 6,066,965, entitled “Method and Apparatus for a N-NARY Logic Circuit Using 1 of 4 Signals” (collectively, “the NDL Patents”), both of which are incorporated by reference for all purposes into this specification. The NDL Patents also disclose NDL implementations of basic logic building blocks such as boolean units and multiplexers. NDL implementations of additional commonly used logic elements (e.g., adders, shifters, multipliers, registers, and RAM devices) are described in U.S. Pat. Nos. 6,301,600; 6,269,387; 6,324,239; 6,275,841; 6,275,838, 6,104,642; and 6,118,716; all of which are incorporated by reference for all purposes into this specification. FAST14 technology uses NDL gates, high-speed static logic storage and transmission techniques, and a novel timing and logic synchronization approach comprising multiple clock domains with overlapping phases, as described in U.S. Pat. No. 6,118,304, entitled “Method and Apparatus for Logic Synchronization” (hereinafter, “the Logic Synchronization Patent”), which is also incorporated by reference for all purposes into this specification.
Because NDL logic is dynamic logic, it is extremely fast but can have some of the power consumption issues commonly associated with dynamic logic. Like traditional dynamic logic, NDL gates require a frequent refresh to hold a logic state, and constantly switching transistors on and off to precharge and then evaluate dynamic logic gates can consume an enormous amount of power. Intrinsity has thus developed several approaches that bgic designers developing designs using FAST14 technology can use to eliminate unnecessary power consumption, including embedding static logic into NDL gates and statically transmitting data across FAST14 logic, both disclosed in U.S. patent application Ser. Nos. 10/187,879 and 10/186,770, respectively. The present invention is yet another method that designers can use to avoid unnecessary power consumption in certain areas and certain versions of NDL logic in FAST14 technology, as described further herein.
The NDL Patents describe the encoding scheme used in multi-wire 1-of-N signals, where the 1-of-N signal's value is encoded according to which specific wire of the multi-wire bundle is asserted. As described in the NDL Patents, the NDL logic family supports a variety of signal encodings. All signals are of the 1-of-N form where N is any integer greater than one. Table 1 demonstrates, using a 1-of-4 signal as an example, the correlation between the 1-of-N signal value (in Table 1, decimal values 0–3) and which of the N wires in the bundle that comprises the 1-of-N signal (wires A[3] through A[0]) is asserted.
TABLE 1(1-of-4)Signal ADecimalValueBinary dit(1-of-4) Signal A wire assertedAvalueA[3]A[2]A[1]A[0]0000001101001021001003111000
As shown in Table 1, and described further in the NDL Patents, a valid 1-of-N signal will never have more than one wire asserted. Similarly, NDL logic requires that a high voltage be asserted on exactly one wire for all values, even 0. Consequently, 1-of-N signals are also referred to as “1-hot” signals, meaning that one and only one wire of the multiwire 1-of-N signal will be asserted for the signal to have a decimal or dit value. The NDL Patents designate a 1-of-N signal with no wires asserted (all wires at a low voltage) as meaning that a value is “unavailable” for the signal. A 1-of-N signal with no wires asserted, meaning that it has no value or an “unavailable” value, is now designated as a “null value” signal, meaning that it is considered a valid signal, but simply has no value. Note that a signal having a null value is not the same as a signal having a logic value of “0”, which occurs when, as shown in Table 1 above, wire A[0] is asserted.
A FAST14 technology based design can be designed to either support and/or actively use null value signals, or it can be designed such that null value signals are considered invalid. In versions that support the use of valid null value signals, the present invention, which includes the introduction and propagation of null value signals through selected NDL gates, can be highly useful to control the overall power consumption of a FAST14 based design, because it enables designers to essentially “power down” unused sections of logic without affecting the docking or synchronization of the logic. Using null value signals in areas of the design that are unused eliminates the need to constantly refresh dynamic data in those areas, where the data would be unused anyway.